# System & Advanced Packaging Design Lead at Phizenix

> Lead signal integrity and advanced packaging design for 200G+ copper interconnects and co-packaged optics across package, PCB and system levels.

- Company: Phizenix (phizenix.com)
- Location: Santa Clara, CA (Hybrid)
- Places: Santa Clara, United States
- Posted: 2026-10-12
- Level: Senior
- Team: System & Advanced Packaging Design
- Work mode: Hybrid
- Apply: https://job-boards.greenhouse.io/phizenix/jobs/5450006008
- Page: https://ye.saranatour.dev/jobs/system-advanced-packaging-design-lead-phizenix-kn7c7w9n118rtg5edx0td7jabx8hnc48

## The posting

System & Advanced Packaging Design Lead
Phizenix · Santa Clara, CA (Hybrid)

**Role Overview**

We are seeking an Advanced 2.5D/3D/Chiplet packaging Lead, who will be directing Signal Integrity for Package, PCB and System design for Copper Interconnects beyond 200G, Work on enabling advanced packaging for Driver, TIA & Optics for AI Scale up engine including SI/ PI, Reliability, Thermals and HVM; Also drive Micro-LED packaging and Heterogeneous package development. Good understanding of OSAT ecosystem and drive the development of complete solutions for data-centers

**Key Responsibilities**

**Technical Leadership & Execution**

- Own package, PCB, and system-level signal integrity architecture for 200G+/lane copper interconnects (C2M, C2C, and cable assemblies) — from channel budgeting and topology definition through post-layout signoff and correlation with silicon measurements.
- Drive 2.5D/3D and heterogeneous package development for co-packaged driver, TIA, and optical engines, including substrate architecture, interposer/bridge evaluation, and die–package co-design with the SerDes and analog design teams.
- Lead micro-LED and photonic packaging development: optical coupling and alignment strategy, hermeticity and reliability, and thermal co-design with the optical engine.
- Define and manage the OSAT and substrate supplier strategy — technology selection, DFM reviews, JEDEC qualification, yield ramp, and HVM readiness.
- Own package-level power integrity and thermal strategy: PDN targets, decoupling plans, lid/TIM selection, and clear signoff criteria across programs.
- Coordinate cross-functional execution across silicon design, product/test engineering, systems hardware, and manufacturing partners; run design reviews and manage schedule and risk.

**Hands-On Design**

- Personally drive substrate stackup definition, ballmap/pinmap optimization, and high-density breakout and escape routing studies for high-speed designs.
- Perform 3D EM extraction and channel simulation (HFSS/Q3D, ADS or equivalent), S-parameter quality checks, and COM/IL/RL budgeting against IEEE 802.3 and OIF-CEI specifications.
- Build and correlate PDN and thermal models spanning die, package, and board.
- Lead lab characterization: VNA/TDR measurements, BER and eye-margin testing, model-to-measurement correlation, and failure analysis support.
- Author package design guidelines, review checklists, and reference collateral used across product programs.

**Required Qualifications**

**Education & Experience**

- Ph.D. in Electrical Engineering (or related) with 5+ years, OR M.S. with 8+ years of Advanced package development in high volume.
- Proven experience leading teams to successful execution, with multiple products delivered in advanced CMOS nodes.

**Core Technical Skills**

- Deep SI/PI expertise for multi-GHz serial links: 112G/224G PAM4 channel design, COM analysis, crosstalk and mode-conversion control, and connector/cable interfaces.
- Advanced packaging depth: FCBGA, RDL/fan-out, 2.5D interposers and silicon bridges, substrate design rules, and materials selection.
- Fluency with industry tools: HFSS, Q3D, SIwave/PowerSI, ADS channel simulation, Cadence APD/Allegro (or equivalent), and thermal tools such as Icepak or FloTHERM.
- Reliability and qualification: JEDEC standards, moisture sensitivity, thermo-mechanical stress, and warpage/coplanarity management for large-body packages.
- Working knowledge of optics packaging: VCSEL/PD or silicon-photoni