Everpure (NYSE: P) has evolved from storage pioneer to data platform, closing fiscal 2026 with $3.7 billion in revenue, its first billion-dollar quarter, and accelerating growth into FY27. Our strategic agenda spans the companies defining the next era of technology - hyperscalers, AI labs, the AI hardware supply chain, data platform providers, and the broader AI ecosystem.

This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us.

THE ROLE

As a Signal Integrity (SI) Engineer, you will support the development and validation of high-performance storage platforms, helping ensure robust electrical performance. You will work with experienced design engineers to help lead electrical modeling, design reviews, lab testing, and issue resolution across the product lifecycle. This role offers the opportunity to build hands-on expertise in SI while collaborating with Hardware Design, PCB Layout, firmware, and manufacturing teams.

WHAT YOU'LL DO

• Support SI across our hardware products for all cutting-edge, high-speed interfaces (e.g., PCIe Gen5+, 800G Ethernet, DDR5), ensuring product reliability and maximizing performance margins from initial link budgets through production release.
• Define global design standards by collaborating with PCB layout, hardware and mechanical teams on stackups, materials, routing rules, and constraints to achieve first-pass success and manufacturing quality across product lines.
• Serve as the SI technical anchor for complex system-level debug, root-cause analysis, and corrective action implementation to resolve critical issues across prototypes, validation, and field escalations.
• Elevate engineering efficiency by developing and standardizing automated simulation flows, reporting pipelines, and Continuous Integration (CI) style checks for model and layout quality across the hardware organization.

WHAT YOU BRING

• Foundational knowledge in high-speed channel design and validation for modern interfaces like PCIe Gen4+, 25G+ SerDes Ethernet, and DDR4/DDR5, with an understanding of electromagnetic concepts, crosstalk mitigation, and jitter analysis.
• Exposure to industry-standard EDA tools (e.g., HyperLynx, Sigrity, Simbeor, HFSS) for pre- and post-layout SI analysis (IBIS-AMI, COM, and channel modeling) and hands-on lab experience using high-speed instruments (VNA, TDR, BERT, Oscilloscopes).
• Ability to work effectively on a cross-functional team, communicate clearly, ask questions, document results, and learn from senior engineers while contributing to technical decisions.
• Experience with scripting or data analysis, preferably using Python, MATLAB, or similar tools to automate analysis, process results, or generate reports.

We are primarily an in-office environment and therefore, you will be expected to work from the Santa Clara, CA office in compliance with Pure’s policies, unless you are on PTO, or work travel, or other approved leave.

#LI-ONSITE

Salary ranges are determined based on role, level and location. For positions open to candidates in multiple geographical locations, the base salary range is reflective of the labor market across the applicable locations.

This role may be eligible for incentive pay and/or equity.

_There is no application deadline and we accept appli